1. Field of the Invention
The present invention relates to a method of forming a conductive pattern of a semiconductor device, and to a method of manufacturing a non-volatile semiconductor memory device using the conductive pattern.
2. Description of the Related Art
Semiconductor memory devices are generally divided into volatile semiconductor memory devices and non-volatile semiconductor memory devices. In the volatile semiconductor memory device, data stored in the cell is dissipated when power is not applied to the device. However, in the non-volatile semiconductor memory device, stored data in the cell is retained even when power is not applied. Because non-volatile semiconductor memory devices can store data for long periods of time, they are used to meet the current high demand for flash semiconductor memory devices such as EEPROMs (electrically erasable and programmable read only memories).
Meanwhile, flash semiconductor memory devices can be generally categorized as stacked flash semiconductor memory devices and split gate flash semiconductor memory devices. The split gate type of flash semiconductor memory device has a structure wherein a floating gate and a control gate are separated from each other, and the floating gate is electrically insulated from the outside. Information is stored in a memory cell of the split gate type of flash semiconductor memory device using the principle that current in a memory cell changes depending on electron injection (programming)/electron discharge (erasing) into/from the floating gate. In the electron injection, hot electrons are injected into the floating gate by a channel hot electron injection (CHEI) mechanism. The electron discharge is accomplished by Fowler-Nordheim (F-N) tunneling through a tunnel insulation layer between the floating gate and the control gate of the split gate type of flash semiconductor memory device. In connection with the electron injection (programming) and electron discharge (erasing), a voltage distribution may be explained as an equivalent capacitor model. Recently, the split gate type of flash semiconductor memory device has been widely used for the purpose of storing data.
FIGS. 1A to 1F illustrate a conventional method of manufacturing a non-volatile semiconductor memory device and, in particular, a split gate type of flash semiconductor device. In the method shown in FIGS. 1A to 1F, the split gate type of flash semiconductor device is not manufactured using a photolithographic process, but by a self-align process.
Referring to FIG. 1A, a first oxide layer 10 and a first conductive layer 20 are formed sequentially on a semiconductor substrate 5, and then a first nitride layer 30 is formed on the first conductive layer 20. The first nitride layer 30 will be patterned to form a floating gate of the flash semiconductor memory device.
The first conductive layer 20 is exposed by partially etching the first nitride layer 30 using a photolithographic process. Then, a second oxide layer 40 is formed on the exposed first conductive layer 20 and the first nitride layer 30.
Referring to FIG. 1B, a spacer 45 is formed on a sidewall of the first nitride layer 30 by etching the second oxide layer 40 using an etch-back process. A portion of the semiconductor substrate 5 is exposed by partially etching the first conductive layer 20 and the first oxide layer 10 using the spacer 45 as an etching mask. Next, impurities are implanted into the exposed portion of the semiconductor substrate 5 to form a source region 50.
Referring to FIG. 1C, the first nitride layer 30 is removed using phosphoric acid to expose the first conductive layer 20 and the first oxide layer 10 beneath the first nitride layer 30. An oxide pattern 15 and a floating gate 25 are formed by removing the exposed portions of the first conductive layer 20 and the first oxide layer 10. Next, a third oxide layer (not shown) is formed of. Then, a second conductive layer 70 that are for is formed on the third oxide layer. In this case, the third oxide layer (not shown) serves as insulation for the second conductive layer 70 and the floating gate 25. A second nitride layer 80 is formed on the second conductive layer 70.
Referring to FIG. 1D, the structure is planarized using a CMP (Chemical Mechanical Polishing) process until the source line 60 contacting the source region 50 is exposed. As a result, the second nitride layer 80 remains on a portion of the second conductive layer 70 disposed adjacent spacer 45. Therefore, upper surfaces of the second conductive layer 70 and the source line 60 that are disposed between the spacer 45 and the remaining portion of the second nitride layer 80 are exposed.
Referring to FIG. 1E, fourth oxide layers 65 and 75 are formed on the second conductive layer 70 and the source line 60 by oxidizing the exposed second conductive layer 70 and the source line 60. Then, the second nitride layer 80 remaining on the second conductive layer 70 is removed by a wet etching process.
Referring to FIG. 1F, a control gate 95 is formed adjacent the floating gate 25 by patterning the second conductive layer 70 using the fourth oxide layers 65 and 75 as etching masks. Here, most of the fourth oxide layers 65 and 75 used as the masks is removed. Then the remaining portions of the fourth oxide layers 65 and 75 are removed by a subsequent cleaning process and a silicidation pretreatment process.
Next, a nitride spacer 92 is formed on a sidewall of the control gate 95. Then, a drain region 90 is formed in the substrate 50 adjacent the control gate 95. A silicidation process and a metallization process are then carried out to form metal wiring 80 above the resultant structure, and a drain contact 82 contacting the drain region 90 is formed to complete the split gate type of flash semiconductor memory device.
However, according to the above-described method, as shown in FIGS. 1C and 1D, due to the CMP process applied used to planarize the second conductive layer 70 is applied to a protruding portion of the second nitride layer 80 (that is, a step). Accordingly, it is difficult to uniformly polish the structure. Therefore, the control gate of the flash semiconductor memory device may not have a uniform upper portion, thereby detracting from the cell efficiency of the semiconductor device.
Japanese Laid-Open Patent Publication No. 2001-023981 discloses a CMP process for forming a uniform film of wiring patterns having different densities on a semiconductor substrate. In the process disclosed in the above-mentioned Japanese Laid-Open Patent Publication, an insulation layer and a photoresist layer are formed on the semiconductor substrate having the wiring patterns, and then the photoresist layer is etched back to form a photoresist pattern on a concave portion of the insulation layer. After the insulation layer is etched using the photoresist pattern as an etching mask, the photoresist pattern is removed. Then, a CMP process is performed on the insulation layer to form a uniform film. However, the control gate or a word line would not have a stable structure because of a difference in the amounts of polishing of a conductive layer due to a polishing protection layer formed on the conductive pattern.